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CY7C144, CY7C145
8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY
Features

Functional Description
The CY7C144 and CY7C145 are high speed CMOS 8K x 8 and 8K x 9 dual-port static RAMs. Various arbitration schemes are included on the CY7C144/5 to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C144/5 can be used as a standalone 64/72-Kbit dual-port static RAM or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). Two flags, BUSY and INT, are provided on each port. BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power down feature is controlled independently on each port by a chip enable (CE) pin or SEM pin.
R/W R CE R OE R
True Dual-Ported Memory Cells that Enable Simultaneous Reads of the same Memory Location 8K x 8 Organization (CY7C144) 8K x 9 Organization (CY7C145) 0.65-Micron CMOS for optimum Speed and Power High Speed Access: 15 ns Low Operating Power: ICC = 160 mA (max.) Fully Asynchronous Operation Automatic Power Down TTL Compatible Master/Slave Select Pin enables Bus Width Expansion to 16/18 Bits or more Busy Arbitration Scheme provided Semaphores included to permit Software Handshaking between Ports INT Flag for Port-to-Port Communication Available in 68-pin PLCC, 64-pin and 80-pin TQFP Pb-free Packages available
Logic Block Diagram
R/W L CE L OE L
(7C145) I/O8L I/O7L I/O0L
I/O CONTROL
I/O CONTROL
I/O 8R(7C145) I/O 7R I/O 0R BUSY R [1, 2] A 12R
[1, 2] BUSYL
A 12L A 0L ADDRESS DECODER MEMORY ARRAY ADDRESS DECODER
A 0R
CEL OEL R/W L SEM L INT L [2]
INTERRUPT SEMAPHORE ARBITRATION
CE R OE R R/W R SEMR INTR [2]
M/S
Notes 1. BUSY is an output in master mode and an input in slave mode. 2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation Document #: 38-06034 Rev. *E
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised April 26, 2009
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CY7C144, CY7C145
Pin Configuration
Figure 1. 68-Pin PLCC (Top View)
IO 1L IO 0L NC [4] OE L R/W L SEM L CEL NC NC VCC A12L A 11L A 10L A9L
Figure 2. 64-Pin TQFP (Top View)
SEML R/WL IO 1L IO 0L A12L A11L A10L OEL CEL NC VCC A9L A8L 52 A7L A6L A5L 49
9876 IO 2L IO 3L IO 4L IO 5L GND IO 6L IO 7L VCC GND IO 0R IO 1R IO 2R VCC IO 3R IO 4R IO 5R IO 6R 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 CY7C144/5 52 51 50 49 48 47 46 45 44
A8L A7L
A6L A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R
64
63
62 61
60
59
58
57
56 55
54
53
IO 2L IO 3L IO 4L IO 5L GND IO 6L IO 7L VCC GND IO 0R IO 1R IO 2R VCC IO 3R IO 4R IO 5R
51 50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
48 47 46 45 44 43 42
A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R
CY7C144
41 40 39 38 37 36 35 34
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43 NC [3] OER A 9R A8R R/W R SEM R CER NC NC GND A12R A 11R A10R A7R A6R
17
18
19 20
21
22
23
24
25 26
27
28
29
30 31 A7R
IO 7R
A5R
R/WR
SEMR
IO 6R
CER NC
A9R
A8R
GND
OER
A12R
Figure 3. 80-Pin TQFP (Top View)
I/O1L I/O0L SEM L R/W L I/O8L A12L A11L OE L CE L NC A10L VCC A9L A8L A7L NC NC A6L NC NC
80
79
78 77
76
75
74
73
72 71
70
69
68
67
66 65
64
63 62
IO 7R
NC I/O 2L I/O 3L I/O 4L I/O 5L GND I/O 6L I/O 7L V CC NC GND I/O0R I/O1R I/O2R V CC I/O 3R I/O 4R I/O 5R I/O 6R NC
1 2 3 4 5 6 7 8
61
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
NC A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R NC NC
9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28
CY7C145
29 30
31
32
33
34
35 36
37
38 39
R/WR
SEMR
I/O7R
CER
GND
A9R
A8R
A7R
A6R
NC
NC NC
NC
OER
A12R
A11R A10R
Notes: 3. I/O8R on the CY7C145. 4. I/O8L on the CY7C145.
Document #: 38-06034 Rev. *E
I/O8R
A5R
NC
40
20
41
A11R A10R
A6R A5R
32
16
33
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Table 1. Selection Guide Description Maximum Access Time Maximum Operating Current Maximum Standby Current for ISB1 Table 2. Pin Definitions Left Port A0L-12L CEL OEL R/WL SEML Right Port A0R-12R CER OER R/WR SEMR Address Lines Chip Enable Output Enable Read/Write Enable Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three least significant bits of the address lines will determine which semaphore to write or read. The I/O0 pin is used when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location. Interrupt Flag. INTL is set when right port writes location 1FFE and is cleared when left port reads location 1FFE. INTR is set when left port writes location 1FFF and is cleared when right port reads location 1FFF. Busy Flag Master or Slave Select Power Ground Description I/O0L-7L(8L) I/O0R-7R(8R) Data bus Input/Output 7C144-15 7C145-15 15 220 60 7C144-25 7C145-25 25 180 40 7C144-35 7C145-35 35 160 30 7C144-55 7C145-55 55 160 30 Unit ns mA mA
INTL BUSYL M/S VCC GND
INTR BUSYR
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Architecture
The CY7C144/5 consists of a an array of 8K words of 8/9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes or reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be used for port-to-port communication. Two semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the CY7C144/5 can function as a Master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The CY7C144/5 has an automatic power down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device.
Master/Slave
An M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This enables the device to interface to a master device with no external components.Writing of slave devices must be delayed until after the BUSY input has settled. Otherwise, the slave chip may begin a write cycle during a contention situation.When presented a HIGH input, the M/S pin allows the device to be used as a master and therefore the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave.
Semaphore Operation
The CY7C144/5 provides eight semaphore latches which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports.The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a 0 to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value is available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a 0), it assumes control over the shared resource, otherwise (reads a 1) it assumes the right port has control and continues to poll the semaphore.When the right side has relinquished control of the semaphore (by writing a 1), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a 1 is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip enable for the semaphore latches (CE must remain HIGH during SEM LOW). A0-2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access.When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a 0 is written to the left port of an unused semaphore, a 1 appears at the same semaphore address on the right port. That semaphore can now only be modified by the side showing 0 (the left port in this case). If the left port now relinquishes control by writing a 1 to the semaphore, the semaphore will be set to 1 for both sides. However, if the right port had requested the semaphore (written a 0) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 5 shows sample semaphore operations. When reading a semaphore, all eight/nine data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore is definitely obtained by one side or the other, but there is no guarantee which side controls the semaphore. Initialization of the semaphore is not automatic and must be reset during initialization program at power up. All Semaphores on both sides should have a one written into them at initialization from both sides to assure that they are free when needed.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge of R/W to guarantee a valid write. A write operation is controlled by either the OE pin (see Figure 8 on page 11) or the R/W pin (see Write Cycle No. 2 waveform). Data can be written to the device tHZOE after the OE is deasserted or tHZWE after the falling edge of R/W. Required inputs for non-contention operations are summarized in Table 3. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must be met before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE are asserted. If the user of the CY7C144/5 wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin.
Interrupts
The interrupt flag (INT) permits communications between ports.When the left port writes to location 1FFF, the right port's interrupt flag (INTR) is set. This flag is cleared when the right port reads that same location. Setting the left port's interrupt flag (INTL) is accomplished when the right port writes to location 1FFE. This flag is cleared when the left port reads location 1FFE. The message at 1FFF or 1FFE is user-defined. See Table 4 for input requirements for INT. INTR and INTL are push-pull outputs and do not require pull-up resistors to operate.
Busy
The CY7C144/5 provides on-chip arbitration to alleviate simultaneous memory location access (contention). If both ports' CEs are asserted and an address match occurs within tPS of each other the Busy logic determines which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not guaranteed which one. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. BUSYL and BUSYR in master mode are push-pull outputs and do not require pull-up resistors to operate.
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CY7C144, CY7C145
Table 3. Non-Contending Read/Write Inputs CE H H X H L L L H L X R/W X H X OE X L H X L X X SEM H L X L H H L High Z Data Out High Z Data In Data Out Data In Outputs I/O0-7/8 Power Down Read Data in Semaphore I/O Lines Disabled Write to Semaphore Read Write Illegal Condition Operation
Table 4. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH) Function R/W Set Left INT Reset Left INT Set Right INT Reset Right INT Table 5. Semaphore Operation Example Function No action Left port writes semaphore Right port writes 0 to semaphore Left port writes 1 to semaphore Left port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore I/O0-7/8 Left 1 0 0 1 1 0 1 1 1 0 1 I/O0-7/8 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left port obtains semaphore Right side is denied access Right port is granted access to semaphore No change. Left port is denied access Left port obtains semaphore No port accessing semaphore address Right port obtains semaphore No port accessing semaphore Left port obtains semaphore No port accessing semaphore Status X X L X CE X L L X Left Port OE X L X X A0-12 X 1FFE 1FFF X INT L H X X R/W L X X X CE L L X L Right Port OE X L X L A0-12 1FFE X X 1FFF INT X X L H
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.[5] Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied.................................................. -55C to +125C Supply Voltage to Ground Potential .................-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .....................................................-0.5V to +7.0V DC Input Voltage[6] ..............................................-0.5V to +7.0V Range Commercial Industrial Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch Up Current .................................................... >200 mA
Operating Range
Ambient Temperature 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 ISB3 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Operating Current Standby Current (Both Ports TTL Levels) Standby Current (One Port TTL Level) GND < VI < VCC Outputs Disabled, GND < VO < VCC VCC = Max., IOUT = 0 mA Outputs Disabled CEL and CER > VIH, f = fMAX[7] CEL or CER > VIH, f = fMAX[7] Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial 125 15 130 60 -10 -10 Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 4.0 mA 2.2 0.8 +10 +10 220 -10 -10 7C144-15 7C145-15 Min 2.4 0.4 2.2 0.8 +10 +10 180 190 40 50 110 120 15 30 100 115 mA mA mA mA Max 7C144-25 7C145-25 Min 2.4 0.4 Max V V V V A A mA Unit
Standby Current Both Ports (Both Ports CMOS Levels) CE and CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0[7] Standby Current (One Port CMOS Level) One Port CEL or CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs, f = fMAX[7]
ISB4
Notes 5. The Voltage on any input or I/O pin cannot exceed the power pin during power up. 6. Pulse width < 20 ns. 7. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3
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Electrical Characteristics
Over the Operating Range (continued) Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 ISB3 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Operating Current Standby Current (Both Ports TTL Levels) Standby Current (One Port TTL Level) GND < VI < VCC Outputs Disabled, GND < VO < VCC VCC = Max., IOUT = 0 mA Outputs Disabled CEL and CER > VIH, f = fMAX[7] CEL or CER > VIH, f = fMAX[7] Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial -10 -10 Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 4.0 mA 2.2 0.8 +10 +10 160 180 30 40 100 110 15 30 90 100 -10 -10 7C144-35 7C145-35 Min 2.4 0.4 2.2 0.8 +10 +10 160 180 30 40 100 110 15 30 90 100 mA mA mA mA Max 7C144-55 7C145-55 Min 2.4 0.4 Max V V V V A A mA Unit
Standby Current Both Ports (Both Ports CMOS Levels) CE and CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0[7] Standby Current (One Port CMOS Level) One Port CEL or CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs, f = fMAX[7]
ISB4
Capacitance
Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 10 15 Unit pF pF
Figure 4. AC Test Loads and Waveforms
5V R1 = 893 OUTPUT C = 30 pF R2 = 347 OUTPUT C = 30pF VTH = 1.4V (a) Normal Load (Load1) (b) Thevenin Equivalent (Load 1) ALL INPUT PULSES OUTPUT C = 30 pF 3.0V GND 10% 90% 90% 10% 3 ns (c) Three-State Delay (Load 3) 5V R1 = 893 OUTPUT C = 5 pF R = 347
RTH = 250
3 ns Load (Load 2)
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Switching Characteristics
Over the Operating Range[8] Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE
[9, 10,11] [9, 10,11]
Description
7C144-15 7C145-15 Min Max
7C144-25 7C145-25 Min 25 Max
7C144-35 7C145-35 Min 35 Max
7C144-55 7C145-55 Min 55 Max
Unit
Read Cycle Time Address to Data Valid Output Hold From Address Change CE LOW to Data Valid OE LOW to Data Valid OE Low to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold From Write End Address Set-Up to Write Start Write Pulse Width Data Set-Up to Write End Data Hold From Write End
[10,11]
15 15 3 15 10 3 10 3 10 0 15 15 12 12 2 0 12 10 0 10 3 30 25
ns 55 ns ns 55 25 ns ns ns 25 ns ns 25 ns ns 55 ns ns ns ns ns ns ns ns ns 25 ns ns 70 40 ns ns
25 3 25 15 3 15 3 15 0 25 25 20 20 2 0 20 15 0 15 3 50 30 3 35 30 30 2 0 25 15 0 0 3 3 3
35 3 35 20 3 20 3 20 0 35 55 45 45 2 0 40 25 0 20 3 60 35
tHZOE tHZCE tPU tPD
tLZCE[9, 10,11]
[9, 10,11] [11] [11]
WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE tWDD
[10,11]
R/W LOW to High Z R/W HIGH to Low Z Write Pulse to Data Delay Write Data Valid to Read Data Valid
[12]
tDDD[12]
Notes 8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOI/IOH and 30-pF load capacitance. 9. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 10. Test conditions used are Load 3. 11. This parameter is guaranteed but not tested. 12. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
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Switching Characteristics
Over the Operating Range Parameter BUSY TIMING[13] tBLA tBHA tBLC tBHC tPS tWB tWH tBDD tINS tINR tSOP tSWRD tSPS BUSY LOW from Address Match BUSY HIGH from Address Mismatch BUSY LOW from CE LOW BUSY HIGH from CE HIGH Port Set-Up for Priority R/W LOW after BUSY LOW R/W HIGH after BUSY HIGH BUSY HIGH to Data Valid
[13] [8]
(continued) 7C144-15 7C145-15 Min Max 15 15 15 15 5 0 13 15 15 15 10 5 5 10 5 5 5 0 20 25 25 25 15 5 5 7C144-25 7C145-25 Min Max 20 20 20 20 5 0 30 35 25 25 20 5 5 7C144-35 7C145-35 Min Max 20 20 20 20 5 0 30 55 35 35 7C144-55 7C145-55 Min Max 30 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns ns
Description
Unit
INTERRUPT TIMING
INT Set Time INT Reset Time SEM Flag Update Pulse (OE or SEM) SEM Flag Write to Read Time SEM Flag Contention Window
SEMAPHORE TIMING
Note 13. Test conditions used are Load 2.
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CY7C144, CY7C145
Switching Waveforms
Figure 5. Read Cycle No. 1 (Either Port Address Access)[14, 15]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Figure 6. Read Cycle No. 2 (Either Port CE/OE Access)[14, 16, 17]
SEM or CE OE tLZOE tLZCE DATA OUT tPU ICC ISB DATA VALID tPD tACE tDOE tHZOE tHZCE
Figure 7. Read Timing with Port-to-Port Delay (M/S=L)[18, 19]
tWC ADDRESSR R/WR MATCH
t PWE
t
SD
t
HD
DATAIN R
VALID
ADDRESSL
MATCH tDDD
DATA OUTL tWDD
VALID
Notes 14. R/W is HIGH for read cycle. 15. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads. 16. Address valid prior to or coincident with CE transition LOW. 17. CEL = L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores. 18. BUSY = HIGH for the writing port. 19. CEL = CER = LOW.
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Switching Waveforms
(continued)
Figure 8. Write Cycle No. 1: OE Three-State Data I/Os (Either Port)[20, 21, 22]
tWC ADDRESS tSCE SEM OR CE tAW R/W tSA DATA IN tPWE tSD DATA VALID tHD tHA
OE tHZOE DATA OUT HIGH IMPEDANCE t
LZOE
Figure 9. Write Cycle No. 2: R/W Three-State Data I/Os (Either Port)[20, 22, 23]
tWC ADDRESS tSCE SEM OR CE tSA tAW tPWE tHA
R/W
tSD DATA IN tHZWE DATA OUT DATAVALID
tHD
tLZWE HIGH IMPEDANCE
Notes 20. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 21. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified tPWE. 22. R/W must be HIGH during all address transitions. 23. Data I/O pins enter high impedance when OE is held LOW during write.
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Switching Waveforms
(continued) Figure 10. Semaphore Read After Write Timing, Either Side[24]
tAA A0-A 2 VALID ADDRESS tAW SEM tSCE tSD I/O0 tSA R/W tSWRD OE WRITE CYCLE tSOP READ CYCLE tDOE DATA IN VALID tPWE tHD DATA OUT VALID tHA tSOP VALID ADDRESS tACE tOHA
Figure 11. Semaphore Contention[25, 26, 27]
A0L-A 2L
MATCH
R/WL SEML tSPS A0R-A 2R MATCH
R/WR SEM R
Notes 24. CE = HIGH for the duration of the above timing (both write and read cycle). 25. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH 26. Semaphores are reset (available to both ports) at cycle start. 27. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
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CY7C144, CY7C145
Switching Waveforms
(continued) Figure 12. Read with BUSY (M/S=HIGH)[19]
tWC ADDRESSR R/WR MATCH tPWE tSD DATAINR tPS ADDRESSL tBLA BUSYL tDDD DATA OUTL tWDD VALID MATCH VALID tHD
tBHA tBDD
Figure 13. Write Timing with Busy Input (M/S=LOW)
tPWE
R/W tWB
BUSY
tWH
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Switching Waveforms
CEL Valid First:
ADDRESSL,R CEL tPS ADDRESS MATCH
(continued) Figure 14. Busy Timing Diagram No. 1 (CE Arbitration)[28]
CER
tBLC BUSYR
tBHC
CER Valid First:
ADDRESSL,R CER tPS ADDRESS MATCH
CEL
tBLC BUSYL
tBHC
Figure 15. Busy Timing Diagram No. 2 (Address Arbitration)[28] Left Address Valid First:
tRC or tWC ADDRESS L ADDRESS MATCH tPS ADDRESS R tBLA BUSY R tBHA ADDRESS MISMATCH
Right Address Valid First:
tRC or tWC ADDRESS R ADDRESS MATCH tPS ADDRESS L tBLA BUSYL tBHA ADDRESS MISMATCH
Note 28. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
Document #: 38-06034 Rev. *E
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Switching Waveforms
Left Side Sets INTR:
ADDRESS L CE L R/W L
(continued) Figure 16. Interrupt Timing Diagrams
tWC WRITE 1FFF tHA [29]
INT R tINS [30]
Right Side Clears INTR:
ADDRESS R CER tINR [30] R/WR OE R
tRC READ 1FFF
INTR
Right Side Sets INTL:
ADDRESS R CE R
tWC WRITE 1FFE tHA [29]
R/W R INT L tINS [30]
Left Side Clears INTL:
ADDRESS R CEL tINR[30] R/WL OEL INTL
Notes 29. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 30. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
tRC READ 1FFE
Document #: 38-06034 Rev. *E
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CY7C144, CY7C145
Figure 17. Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.2 NORMALIZED ICC, ISB 1.0 0.8 0.6 0.4 0.2 0.6 -55 25 125 ISB3 VCC = 5.0V VIN = 5.0V ICC OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 200 160 120 80 40 0 5.0 VCC = 5.0V TA = 25C
1.4 NORMALIZED ICC, ISB 1.2 1.0 0.8 0.6 0.4 0.2
ICC ISB3
0.0 4.0
OUTPUT SOURCE CURRENT (mA)
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE
4.5
5.0
5.5
6.0
0
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C)
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT (mA)
NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED tAA NORMALIZED tAA 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 TA = 25C
NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.6 1.4 1.2 1.0 VCC = 5.0V 0.8 0.6 -55
140 120 100 80 60 40 20
OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE
VCC = 5.0V TA = 25C 1.0 2.0 3.0 4.0 5.0
25
125
0 0.0
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C)
OUTPUT VOLTAGE (V)
TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 1.00 NORMALIZED tPC 30.0 25.0 DELTA tAA (ns) 20.0
TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING
1.25 NORMALIZED ICC
NORMALIZED ICC vs. CYCLE TIME VCC = 5.0V TA = 25C VIN = 5.0V
0.75 0.50
1.0
15.0 10.0 5.0 VCC = 4.5V TA = 25C 0 200 400 600 800 1000
0.75
0.25 0.0
0
1.0
2.0
3.0
4.0
5.0
0
0.50 10
28
40
66
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Document #: 38-06034 Rev. *E
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Ordering Information
8K x8 Dual-Port SRAM
Speed (ns) 15 Ordering Code CY7C144-15AC CY7C144-15AXC CY7C144-15JC CY7C144-15JXC CY7C144-15AI CY7C144-15JXI CY7C144-15AXI 25 CY7C144-25AC CY7C144-25AXC CY7C144-25JC CY7C144-25AI CY7C144-25JI 35 CY7C144-35AC CY7C144-35JC CY7C144-35AI CY7C144-35JI 55 CY7C144-55AC CY7C144-55AXC CY7C144-55JC CY7C144-55JXC CY7C144-55AI CY7C144-55JI Package Diagram 51-85046 51-85046 51-85005 51-85005 51-85046 51-85005 51-85046 51-85046 51-85046 51-85005 51-85046 51-85005 51-85046 51-85005 51-85046 51-85005 51-85046 51-85046 51-85005 51-85005 51-85046 51-85005 51-85065 51-85065 51-85005 51-85065 51-85005 51-85065 51-85005 51-85065 51-85005 51-85005 51-85065 51-85005 51-85065 51-85005 51-85065 51-85005 Package Type 64-Pin Thin Quad Flat Pack 64-Pin Thin Quad Flat Pack (Pb-Free) 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier (Pb-Free) 64-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier (Pb-Free) 64-Pin Thin Quad Flat Pack (Pb-Free) 64-Pin Thin Quad Flat Pack 64-Pin Thin Quad Flat Pack (Pb-Free) 68-Pin Plastic Leaded Chip Carrier 64-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier 64-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier 64-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier 64-Pin Thin Quad Flat Pack 64-Pin Thin Quad Flat Pack (Pb-Free) 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier (Pb-Free) 64-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier 80-Pin Thin Quad Flat Pack 80-Pin Thin Quad Flat Pack (Pb-Free) 68-Pin Plastic Leaded Chip Carrier 80-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier 80-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier 80-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier 68-Pin Plastic Leaded Chip Carrier (Pb-Free) 80-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier 80-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier 80-Pin Thin Quad Flat Pack 68-Pin Plastic Leaded Chip Carrier Industrial Commercial Industrial Commercial Industrial Commercial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Operating Range Commercial
8K x9 Dual-Port SRAM
15 CY7C145-15AC CY7C145-15AXC CY7C145-15JC 25 CY7C145-25AC CY7C145-25JC CY7C145-25AI CY7C145-25JI 35 CY7C145-35AC CY7C145-35JC CY7C145-35JXC CY7C145-35AI CY7C145-35JI 55 CY7C145-55AC CY7C145-55JC CY7C145-55AI CY7C145-55JI
Document #: 38-06034 Rev. *E
Page 17 of 20
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Package Diagrams
Figure 18. 64-Pin Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm), 51-85046
51-85046 *C
Document #: 38-06034 Rev. *E
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Package Diagrams
(continued) Figure 19. 80-Pin Thin Plastic Quad Flat Pack, 51-85065
51-85065-*B
Figure 20. 68-Pin Plastic Leaded Chip Carrier, 51-85005
51-85005-*A
Document #: 38-06034 Rev. *E
Page 19 of 20
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Document History Page
Document Title: CY7C145, CY7C144 8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Document Number: 38-06034 Rev. ** *A *B *C ECN No. 110175 122285 236752 393320 Orig. of Change SZV RBI YDT YIM Submission Description of Change Date 09/29/01 12/27/02 See ECN See ECN Change from Spec number: 38-00163 to 38-06034 Power up requirements added to Maximum Ratings Information Removed cross information from features section, added CY7C144-15AI to ordering information section Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C144-15AXC, CY7C144-15JXC, CY7C144-15AXI, CY7C144-25AXC, CY7C144-55AXC, CY7C144-55JXC, CY7C145-15AXC, CY7C145-35JXC
*D *E
2623658 2699693
VKN/PYRS VKN/PYRS
12/17/2008 Added CY7C144-15JXI in the Ordering information table 04/29/2009 Corrected defective Logic Block diagram, Pinouts and Package diagrams
Sales, Solutions and Legal Information
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(c) Cypress Semiconductor Corporation, 2005-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-06034 Rev. *E
Revised April 26, 2009
Page 20 of 20
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